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| KM23V64000T 64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM FEATURES * Switchable organization 8,388,608 x 8(byte mode) 4,194,304 x 16(word mode) * Fast access time 3.3V Operation : 120ns(Max.) 3.0V Operation : 150ns(Max.) * Supply voltage : single +3.0V/ single +3.3V * Current consumption Operating : 40/35mA(Max.) Standby : 30A(Max.) * Fully static operation * All inputs and outputs TTL compatible * Three state outputs * Package : KM23V64000T : 44-TSOP2-400 CMOS MASK ROM GENERAL DESCRIPTION The KM23V64000T is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 8,388,608 x 8 bit(byte mode) or as 4,194,304 x 16 bit(word mode) depending on BHE voltage level.(See mode selection table) This device operates with 3.0V or 3.3V power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The KM23V64000T is packaged in a 44-TSOP2. FUNCTIONAL BLOCK DIAGRAM A21 . . . . . . . . A0 A-1 ... CE OE BHE CONTROL LOGIC Q0/Q8 Q7/Q15 X BUFFERS AND DECODER MEMORY CELL MATRIX (4,194,304x16/ 8,388,608x8) PIN CONFIGURATION A21 A18 A17 A7 A6 A5 1 2 3 4 5 6 7 8 9 11 44 A20 43 A19 42 A8 41 A9 40 A10 39 A11 38 A12 37 A13 36 A14 35 A15 Y BUFFERS AND DECODER SENSE AMP. BUFFERS A4 A3 A2 A0 A1 10 TSOP2 34 A16 33 BHE 32 VSS 31 Q15/A-1 30 Q7 29 Q14 28 Q6 27 Q13 26 Q5 25 Q12 24 Q4 23 VCC CE 12 VSS 13 OE 14 Q0 15 Q8 16 Q1 17 Q9 18 Q2 19 Q10 20 Q3 21 Pin Name A0 - A21 Q0 - Q14 Q15 /A-1 BHE CE OE VCC VSS Pin Function Address Inputs Data Outputs Output 15(Word mode)/ LSB Address(Byte mode) Word/Byte selection Chip Enable Output Enable Power Ground Q11 22 KM23V64000T KM23V64000T ABSOLUTE MAXIMUM RATINGS Item Voltage on Any Pin Relative to VSS Temperature Under Bias Storage Temperature Symbol VIN TBIAS TSTG Rating -0.3 to +4.5 -10 to +85 -55 to +150 CMOS MASK ROM Unit V C C Remark - NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to th e conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extendd periods may e affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to VSS, TA=0 to +70C) Item Supply Voltage Supply Voltage Symbol VCC VSS Min 2.7/3.0 0 Typ 3.0/3.3 0 Max 3.3/3.6 0 Unit V V DC CHARACTERISTICS Parameter Operating Current Standby Current(TTL) Standby Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All Inputs Input Low Voltage, All Inputs Output High Voltage Level Output Low Voltage Level Symbol ICC ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOH=-400A IOL=2.1mA Test Conditions CE=OE=VIL , all outputs open VCC=3.3V0.3V VCC=3.0V0.3V Min Max 40 35 500 30 2.0 -0.3 2.4 10 10 VCC+0.3 0.6 0.4 Unit mA mA A A A A V V V V CE=VIH, all outputs open CE=VCC, all outputs open VIN=0 to VCC VOUT=0 to VCC NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(V is VCC+0.3V which, during transitions, may overshoot to V IH) CC+2.0V for periods <20ns. MODE SELECTION CE H L L OE X H L BHE X X H L Q15/A-1 X X Output Input Mode Standby Operating Operating Operating Data High-Z High-Z Q0~Q15 : Dout Q0~Q7 : Dout Q8~Q14 : High-Z Power Standby Active Active Active CAPACITANCE(TA=25C, f=1.0MHz) Item Output Capacitance Input Capacitance Symbol COUT CIN Test Conditions VOUT=0V VIN=0V MIN Max 12 12 Unit pF pF NOTE : Capacitance is periodically sampled and not 100% tested. KM23V64000T AC CHARACTERISTICS (VCC=3.3V/3.0V0.3V, unless otherwise noted.) TEST CONDITIONS Item Input Pulse Levels Input Rise and Fall Times Input and Output timing Levels Output Loads Value CMOS MASK ROM 0.45V to 2.4V 10ns 1.5V 1 TTL Gate and CL=100pF READ CYCLE Item Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Output or Chip Disable to Output High-Z Output Hold from Address Change Symbol tRC tACE tAA tOE tDF tOH 0 VCC=3.3V0.3V Min 120 120 120 60 20 0 Max VCC=3.0V0.3V Min 150 150 150 70 30 Max Unit ns ns ns ns ns ns TIMING DIAGRAM READ ADD A0~A21 A-1(*1) tACE CE tOE OE ADD1 tRC ADD2 tDF(*3) tAA tOH DOUT D0~D7 D8~D15(*2) VALID DATA VALID DATA NOTES : *1. Byte Mode only. A-1 is Least Significant Bit Address.(BHE = V IL) *2. Word Mode only.(BHE=VIH) *3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V or VOL level. OH KM23V64000T PACKAGE DIMENSIONS 44-TSOP2-400 CMOS MASK ROM 0~8 0.25 ( ) 0.010 #44 #23 0.45 ~0.75 0.018 ~ 0.030 11.760.20 0.4630.008 10.16 0.400 ( 0.50 ) 0.020 #1 #22 1.000.10 0.0390.004 1.20 MAX. 0.047 + 0.10 - 0.05 + 0.004 0.006 - 0.002 0.15 18.81 MAX. 0.741 18.410.10 0.7250.004 ( 0.805 ) 0.032 0.350.10 0.0140.004 0.80 0.0315 0.05 MIN. 0.002 0.10 MAX 0.004 |
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